Committee:

Jason T. Stauth, Ph.D. (Chair)

Charles R. Sullivan, Ph.D.

Geoffrey P. Luke, Ph.D.

David J. Perreault, Ph.D.

Abstract:

Power management and delivery is a growing challenge across a wide range of areas spanning performance and mobile computing, communications, renewable energy, automotive, and a variety of other applications. In common among all these platforms is a push to decrease overall size, increase performance, and reduce power consumption. With digital processing benefiting greatly from exponential transistor scaling, the ability to meet the requirements of modern and future electronics is now largely dependent upon the ability to scale power electronics, whose area and volume are dominated by passive energy storage elements, especially inductors.

Hybrid-resonant switched capacitor converters combine the high energy density of capacitors with small inductance to improve passive component utilization, enable output regulation, and provide alleviated inductance requirements that are well-suited for integration. Furthermore, these benefits can be enhanced with the implementation of merged-LC resonators that combine capacitive and inductive energy storage. Merging passive energy storage reduces area overhead to increase power density and improves conductor utilization, decreasing both DC and AC conduction losses in the structure to increase efficiency.

This work focuses on the design and implementation of efficient high-density DC-DC converters using a variety of hybrid-resonant switched capacitor architectures with merged-LC resonators. Fundamental converter analysis provides operating principles, modeling strategies, and optimization techniques for hybrid converters that result in a minimum achievable total loss metric used to compare different topologies. Results are verified experimentally and compared to the state-of-the-art using multiple discrete-component and fully integrated converters. Two monolithic converters with merged-LC resonators and nominal 2:1 and 3:1 conversion ratios are implemented in 180nm CMOS, achieving 85.5% and 78.3% efficiency, respectively. The converters feature variable output voltage regulation and fast transient response, with the latter leveraging on-chip magnetics to monitor powertrain current and provide closed-loop resonant switching frequency regulation.