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Meeting ID: 995 9695 0090  
Passcode: 153207

With the impending end of Moore’s Law nearing ever closer, alternate avenues for continued performance scaling in computing systems are being aggressively pursued from various angles. The energy consumption of pervasive workloads such as deep learning in data centers and high-performance computers has reached an environmentally-significant level and will continue to worsen without significant intervention. Optical solutions have been widely accepted as an enabling path forward, initially in the form of optical interconnects to connect spatially-distanced compute nodes and further term as dedicated photonic deep learning accelerators and photonic quantum computers. All of these applications require high-performance photonic chips with comparable production scale to microelectronics chips, both in terms of device density and total wafer throughput. Silicon photonics provides the most promising platform for satisfying these requirements through leveraging the same mature complementary metal-oxide-semiconductor (CMOS) infrastructure used to fabricate modern electronic chips. Crucially, the high refractive index contrast of silicon and silicon dioxide enables micron-scale devices with unparalleled density, allowing for chips with tens to hundreds of thousands of optical devices.

In this talk, I will first discuss recent efforts to enable ultra-energy-efficient, ultra-high-bandwidth silicon photonic interconnects capable of communicating over a terabit per second on a single fiber while consuming as low as 200 femtojoules of energy per bit. I will then outline significant efforts in device optimization in collaboration with a commercial 300 mm CMOS foundry to enable a comprehensive process design kit (PDK) which can be easily tailored in an application-specific manner to build state-of-the-art systems for a broad range of applications. Finally, I conclude with compelling future directions opened by this PDK in quantum photonics and photonic neural networks, which provide a clear roadmap for environmentally-conscious scaling of computing systems in the post-Moore’s Law era.