Optional ZOOM LINK
Meeting ID: 935 8655 7757
Passcode: 008066

The rapid rise of data-intensive workloads, driven by artificial intelligence, is exposing the fundamental energy and latency limits of conventional computing hardware. The memory wall bottleneck, in particular, demands a shift toward new hardware architectures designed to minimize costly data movement.

In this seminar, I will present advances at the intersection of materials science and device engineering that address this challenge. First, I will discuss adaptive oxide-based resistive memories for in-memory computing, detailing how novel MAX-phase electrodes achieve record-low off-state currents and how an in-situ recovery method enables robust transfer learning on analog AI accelerators. Next, I will introduce complementary back-end-of-line technologies that advance scalability for high-density, on-chip memory, including oxide semiconductor gain-cells and an interface-dipole engineering strategy for precise threshold voltage tuning. Together, these results highlight a practical and scalable path toward vertically integrated, energy-efficient electronics for future data-centric applications.

Hosted by Professor Cong Chen